The present invention relates to graphics memory architectures, and particularly to architectures optimized for both video-driven and 3D-graphics-driven performance.
A standard graphics memory organization stores data for a scanline at sequential addresses. This is convenient for the display of data, which has to be accessed in scanline order, but is inefficient for drawing operations.
The performance of drawing often depends on maintaining locality of data. This may be due to caches or to the row/column organization of dynamic memories. Drawing operations rarely stay on the same scanline for long and generally move in Y as well as X. Organizing memory for efficient access only in the X dimension degrades overall performance.
Planar Byte Memory Organization with Linear Access
The present application discloses an improvement on a graphics memory architecture which is oriented in a tiled format. (In the preferred system example, memory is organized as 8 byte by 8 byte tiles that are stacked through memory; and data is accessed by tile number instead of by byte position.) The present application discloses an improvement wherein the memory controller can operate selectably, for each access, in two modes:    either providing parallel access to a single tile (which is more advantageous for many graphics applications),    or providing parallel access to a scanline which extends across many tiles (which is more advantageous for many video applications).Preferably this is achieved, in part, by an adjustment of row address locations and address connections.
FIGS. 1A and 1B, in combination, show a block diagram of the core of a graphics accelerator which includes many innovations. FIG. 1C shows the transform and lighting subsystem of this accelerator, FIG. 1D shows the arrangement of the components of a Texture Pipe in this accelerator, and FIG. 1E shows the interface to the Memory Pipe Unit in this accelerator.